Related to the SPM courses, different thesis arguments are available, under supervision of course professor, including:
The main goal of the thesis is the implementation of a generic macro data flow engine suitable to a) represent b) transform and c) efficiently execute macro data flow graphs on multi/many core shared memory architectures. In particular: • An high level representation of the macro data flow graphs must be designed, where macro data flow instructions are represented as function, input token list, output destination list triples with some kind of representation suitable to use any “function” written in the host programming language (C, C++) as the function to be computed. • Suitable tools supporting macro data flow rewriting should be implemented, suitable to support the application programmer in the tuning of the application macro data flow code, and • An efficient interpreter of macro data flow graphs has to be implemented, possibly exploiting all the interesting features of the underlying architecture (e.g. presence of co-processors (GPU, MIC), NUMA features, cache coherence mechanisms peculiarities). Possible issues specifically developed in the reference courses: In the SPM course, specific activities concerning the macro data flow model may be assigned to the student, partially fulfilling the requirements of the “course project”. In the SPD course, aspects related to the exploitation of GPU and MIC coprocessors may be considered as integral part of the course project.
The thesis aims at developing a structured parallel programming framework in Erlang, suitable to execute parallel Erlang applications on networked multicore Linux workstations. The implementation of the structured parallel programming framework will leverage the primitive and efficient mechanisms provided by Erlang to implement processes and the related message passing primitives as well as to implement cooperating instances of the Erlang interpreter on internetworked workstations. The thesis will start from preliminary experiments, prototypes and achievements from the ParaPhrase EU FP7 STREP project. The validation of the framework will be performed using workstations currently at the Dept. of Computer Science including Infiniband interconnected Xeon multicore, GPU (Tesla, Kepler) equipped workstations and Xeon PHI equipped workstations. Possible issues specifically developed in the reference courses: Within the SPM course, the possibility to develop a project in Erlang rather than using the frameworks usually taken into account for the course will be considered, such that preliminary knowledge of Erlang could be acquired by the student during the course project.
The main goal of the thesis is the development of a library of high level parallel design patterns on top of Intel TBB and OpenMP, implemented as algorithmic skeleton, that is ready to use object classes implementing the patterns on top of multi/many core architectures. Both TBB and OpenMP de facto already provide some specific patterns (e.g. the pipeline pattern in TBB or “kind of” map pattern (parallel for) in OpenMP). The idea here is to provide an homogeneous, general set of skeletons implementing the nonexistent patterns or wrapping the existent ones in uniform pattern class, with the final goal of providing the application programmer with a consistent and efficient set of patterns to implement applications on top of a wide range of different shared memory multi core architectures. As a secondary goal, the thesis will investigate the possibility to run part of the application skeletons (or part of a single skeleton) on MIC style coprocessors (e.g. Xeon PHI) in case one or more of these devices are present. Possible issues specifically developed in the reference courses: SPD course will consider to assign specific tasks relative to Xeon PHI programming with TBB/OpenMP to the student, in such a way the preliminary background needed to exploit this architecture is acquired during the project course.
The main goal of the thesis is the development of a framework supporting the execution of FastFlow structured programs on a set of multicore cloud computing nodes, possibly equipped with GPUs. The thesis will build on already existing prototypes demonstrating the feasibility of the deployment of FastFlow virtual machines on cloud nodes implementing workers of a centrally managed task farm. The thesis will manage to implement: * A generalized mechanism for the deployment of FastFlow virtual machines on the cloud * Suitable tools to support the automatic creation of virtual machine images from the original, non cloud specific, FastFlow program * Suitable tools to reconfigure the set of cloud deployed virtual machines if needed (e.g. adding more resources or getting rid of part of the already recruited resources, in case of load increase/decrease in the application or in case of under/over performing of the assigned resources). The thesis will be assigned in the framework of the activities related to the FP7 EU STREP project ParaPhrase. Possible issues specifically developed in the reference courses: PAD activities/project assigned to the student will include topics such that the student may acquire the preliminary knowledge needed to tackle with the thesis goals. In particular, specific activities related to the automated deployment of an orchestrated set of virtual machines on the cloud resources will be investigated. SPM course will provide the FastFlow background necessary to deal with the thesis structured parallel programming topics.